Any-layer HDI describes constructions that provide flexible layer-to-layer interconnection through successive microvia structures. ELIC is commonly expanded as every-layer interconnect. These terms describe an architecture; they do not mean that every routing choice is manufacturable or that every supplier interprets the shorthand identically.
Replace the label with a drawing
Define which layer pairs can connect, which connections can be stacked, and which restrictions apply near pads or other features. Ask the supplier to identify the approved material and copper-filling route. The purchasing document should describe the actual structure rather than relying only on “ELIC” as a complete specification.
The attraction is routing freedom in dense designs. The tradeoff is a construction that can depend heavily on coordinated lamination, registration and interconnect preparation. A useful design review demonstrates why a simpler build-up architecture cannot meet the requirement before committing to the more involved option.
Architecture review matrix
| Question | Evidence to prepare |
|---|---|
| Where is extra layer access needed? | A map of blocked routes under the actual device footprint |
| Which connections carry critical signals? | A transition model with reference planes and return paths |
| What is the assembly exposure? | Planned reflow, rework and other relevant thermal events |
| How is the process demonstrated? | Representative construction and agreed acceptance evidence |
Avoid local optimization
A route that is short in the layout editor may still require a difficult physical transition. Likewise, reducing overall board area can make inspection access, heat removal or repair more difficult. Evaluate the full product envelope, including shielding, connectors and test access, before treating board area as the only measure of success.
For a design with one unusually dense device, consider whether the device placement, package choice or localized routing strategy can reduce the need for unrestricted interconnection. This is an engineering comparison, not a rule that ELIC should always be avoided. A documented routing requirement is the basis for the choice.
Approve a reproducible configuration
Require a named stackup revision, material construction and via arrangement. Agree which changes trigger renewed engineering review. A substitute that preserves the layer count can still change interconnect reliability or electrical behavior.
Use a prototype to test the manufacturing and assembly questions that matter for the final product. Preserve the construction and process records alongside electrical results. If the later production supplier or process changes, review whether the original evidence still represents the new build. This site does not claim an any-layer production capability without supporting client information.
Continue the engineering review
- HDI PCB stackup selection
- mSAP PCB fabrication
- Microvia reliability and thermal exposure
- HDI PCB engineering hub
Review your HDI requirements
Share the board revision, proposed stackup, quantity and open questions. Include the requirements discussed in this guide so the project review starts with the same assumptions.