pin package delay and via delay in high speed length tuning

What are Pin and Via Delays?

In high-speed digital designs, the delay introduced by the pins of the integrated circuit (IC) package and the vias on the printed circuit board (PCB) can significantly impact the overall signal integrity and timing. These delays, known as pin package delay and via delay, must be carefully considered and compensated for during the length tuning process to ensure optimal performance of the system.

Pin Package Delay

Pin package delay refers to the time taken for a signal to propagate from the die of the IC to the pins of the package. This delay is caused by the capacitance and inductance of the package leads, as well as the bond wires that connect the die to the package. The pin package delay can vary depending on the type of package, such as quad flat pack (QFP), ball grid array (BGA), or chip scale package (CSP).

The pin package delay can be modeled using an equivalent circuit consisting of resistors, capacitors, and inductors. The values of these components depend on the package geometry, material properties, and the frequency of operation. Table 1 shows typical values of pin package delay for different package types.

Package Type	Pin Package Delay (ps)
QFP	50-100
BGA	20-50
CSP	10-30

Table 1: Typical pin package delay values for different package types.

Via Delay

Via delay refers to the time taken for a signal to propagate through a via on the PCB. Vias are used to connect different layers of the PCB and are essential for routing signals in complex designs. However, vias introduce discontinuities in the signal path, which can cause reflections and degrade the signal quality.

The via delay depends on several factors, such as the via geometry, the dielectric material of the PCB, and the frequency of operation. The via geometry includes the via diameter, the pad size, and the anti-pad size. The dielectric material determines the characteristic impedance of the via, which affects the signal propagation speed.

Table 2 shows typical values of via delay for different PCB materials and via geometries.

PCB Material	Via Diameter (mil)	Via Delay (ps)
FR-4	10	10-20
Rogers	10	5-10
FR-4	20	20-30
Rogers	20	10-15

Table 2: Typical via delay values for different PCB materials and via geometries.

Request PCB Manufacturing & Assembly Quote Now

Impact of Pin and Via Delays on High-Speed Designs

Signal Integrity

Pin package delay and via delay can have a significant impact on the signal integrity of high-speed designs. These delays introduce discontinuities in the signal path, which can cause reflections and degrade the signal quality. Reflections occur when there is an impedance mismatch between the signal path and the load, causing a portion of the signal energy to be reflected back to the source.

Reflections can cause several problems, such as:

Overshoot and undershoot: When the reflected signal adds to the incident signal, it can cause the signal level to exceed the maximum or minimum threshold, leading to overshoot or undershoot.
Ringing: The reflected signal can oscillate back and forth between the source and the load, causing ringing in the signal waveform.
Inter-symbol interference (ISI): The reflections from one bit can interfere with the subsequent bits, causing ISI and reducing the eye opening of the signal.

To minimize the impact of reflections, it is essential to match the impedance of the signal path to the load impedance. This can be achieved by using appropriate termination techniques, such as series termination or parallel termination.

Timing

Pin package delay and via delay can also affect the timing of high-speed designs. These delays add to the overall propagation delay of the signal, which can cause timing violations and reduce the maximum operating frequency of the system.

In synchronous designs, where the data is transferred on the rising or falling edge of a clock signal, the pin package delay and via delay can cause the data to arrive at the receiver later than expected. This can lead to setup or hold time violations, where the data is not stable when the clock edge arrives.

To compensate for the pin package delay and via delay, designers use techniques such as:

Delay matching: The length of the signal traces is adjusted to match the delay of the longest path, ensuring that all signals arrive at the receiver at the same time.
Phase-locked loops (PLLs): PLLs are used to generate a clock signal that is phase-aligned with the data, compensating for the delay introduced by the package and PCB.
Equalization: Equalization techniques, such as pre-emphasis and de-emphasis, are used to compensate for the frequency-dependent loss of the channel, improving the signal quality at the receiver.

Length Tuning for Pin and Via Delay Compensation

Length tuning is a technique used to compensate for the pin package delay and via delay in high-speed designs. The goal of length tuning is to match the delay of all signal paths, ensuring that the data arrives at the receiver at the same time.

Delay Calculation

The first step in length tuning is to calculate the delay introduced by the pin package and vias. This can be done using electromagnetic (EM) simulation tools or analytical models.

EM simulation tools, such as Ansys HFSS or Cadence Sigrity, can accurately model the package and PCB geometry and calculate the delay introduced by the pins and vias. These tools solve Maxwell’s equations numerically to determine the electromagnetic fields and currents in the structure.

Analytical models, such as the cavity model or the transmission line model, can provide a quick estimate of the pin package delay and via delay. These models use simplified geometries and assumptions to calculate the equivalent circuit parameters of the package and PCB.

Table 3 shows a comparison of the delay values obtained using EM simulation and analytical models for a BGA package and a 10-mil via in FR-4.

Method	BGA Package Delay (ps)	Via Delay (ps)
EM Simulation	35	12
Analytical Model	30	15

Table 3: Comparison of delay values obtained using EM simulation and analytical models.

Delay Compensation

Once the pin package delay and via delay are known, the next step is to compensate for these delays by adjusting the length of the signal traces on the PCB. The goal is to match the delay of all signal paths, ensuring that the data arrives at the receiver at the same time.

There are two main approaches to delay compensation:

Pre-layout tuning: In this approach, the delay is compensated for during the initial layout of the PCB. The designer estimates the pin package delay and via delay based on the package and PCB specifications and adjusts the length of the signal traces accordingly.
Post-layout tuning: In this approach, the delay is compensated for after the initial layout is complete. The designer simulates the PCB using EM simulation tools or analytical models to determine the actual delay of each signal path. The length of the signal traces is then adjusted to match the delay of the longest path.

Post-layout tuning is more accurate than pre-layout tuning because it takes into account the actual geometry and material properties of the PCB. However, it requires additional simulation time and may require multiple iterations to achieve the desired delay matching.

Table 4 shows an example of delay compensation using post-layout tuning for a high-speed DDR4 interface.

Signal	Uncompensated Delay (ps)	Compensated Delay (ps)
CLK	100	100
DATA[0]	90	100
DATA[1]	95	100
DATA[2]	105	100
DATA[3]	110	100

Table 4: Example of delay compensation using post-layout tuning for a DDR4 interface.

Best Practices for Pin and Via Delay Management

To minimize the impact of pin package delay and via delay on high-speed designs, designers should follow some best practices:

Choose the appropriate package: Select a package that minimizes the pin package delay, such as BGA or CSP, instead of QFP.
Optimize the via geometry: Use small via diameters and pad sizes to minimize the via delay. Avoid using unnecessary vias and optimize the via placement to reduce the signal path length.
Use appropriate PCB materials: Choose PCB materials with low dielectric constant and loss tangent, such as Rogers or Isola, to minimize the via delay and signal attenuation.
Use EM simulation tools: Perform EM simulations of the package and PCB to accurately determine the pin package delay and via delay. Use these results to guide the length tuning process.
Perform post-layout tuning: Perform post-layout tuning to compensate for the actual delay of each signal path. Use EM simulation tools or analytical models to determine the delay and adjust the signal trace lengths accordingly.
Use equalization techniques: Use equalization techniques, such as pre-emphasis and de-emphasis, to compensate for the frequency-dependent loss of the channel and improve the signal quality at the receiver.
Monitor the signal integrity: Use signal integrity analysis tools, such as eye diagrams and bit error rate (BER) measurements, to monitor the quality of the signal and ensure that it meets the required specifications.

Conclusion

Pin package delay and via delay are critical factors that must be considered in high-speed digital designs. These delays can significantly impact the signal integrity and timing of the system, leading to reflections, ISI, and timing violations.

To compensate for the pin package delay and via delay, designers use length tuning techniques, such as pre-layout tuning and post-layout tuning. These techniques involve adjusting the length of the signal traces on the PCB to match the delay of all signal paths.

To minimize the impact of pin package delay and via delay, designers should follow best practices such as choosing the appropriate package, optimizing the via geometry, using appropriate PCB materials, and performing EM simulations and post-layout tuning.

By carefully managing the pin package delay and via delay, designers can ensure that their high-speed designs meet the required performance and reliability specifications.

FAQ

What is pin package delay?
Pin package delay refers to the time taken for a signal to propagate from the die of the IC to the pins of the package. It is caused by the capacitance and inductance of the package leads and bond wires.
What is via delay?
Via delay refers to the time taken for a signal to propagate through a via on the PCB. Vias are used to connect different layers of the PCB and can introduce discontinuities in the signal path, causing reflections and degrading the signal quality.
How do pin package delay and via delay affect high-speed designs?
Pin package delay and via delay can affect the signal integrity and timing of high-speed designs. They can cause reflections, overshoot, undershoot, ringing, and inter-symbol interference (ISI), degrading the signal quality. They can also cause timing violations and reduce the maximum operating frequency of the system.
What is length tuning?
Length tuning is a technique used to compensate for the pin package delay and via delay in high-speed designs. It involves adjusting the length of the signal traces on the PCB to match the delay of all signal paths, ensuring that the data arrives at the receiver at the same time.
What are some best practices for managing pin package delay and via delay?
Some best practices for managing pin package delay and via delay include choosing the appropriate package, optimizing the via geometry, using appropriate PCB materials, performing EM simulations and post-layout tuning, using equalization techniques, and monitoring the signal integrity.