Key Features of the 4017
The 4017 decade counter/divider IC has several useful features:
- 10 decoded outputs (Q0-Q9)
- Positive edge triggered clock input
- Enable input for counting
- Reset input to reset count to 0
- Carry out signal when counter reaches 9
- Wide supply voltage range (3V to 15V)
- Low power consumption
- High noise immunity
These features make the 4017 suitable for a variety of sequential logic and timing applications. Some example uses include:
- Generating timing signals
- Sequencing LEDs or other outputs
- Frequency division
- Event counting
- Making a simplified VU Meter
- Generating time delays
4017 Pinout and Pin Functions
The 4017 is available in 16-pin DIP and SOIC surface mount packages. Here is the pinout for the DIP package:
| Pin | Name | Function |
|---|---|---|
| 1 | Q5 | Decoded output 5 |
| 2 | Q1 | Decoded output 1 |
| 3 | Q0 | Decoded output 0 |
| 4 | Q2 | Decoded output 2 |
| 5 | Q6 | Decoded output 6 |
| 6 | Q7 | Decoded output 7 |
| 7 | Q3 | Decoded output 3 |
| 8 | GND | Ground (0V) |
| 9 | Q8 | Decoded output 8 |
| 10 | Q4 | Decoded output 4 |
| 11 | Q9 | Decoded output 9 |
| 12 | CARRY | Carry out (goes high when Q9 is high) |
| 13 | ENABLE | Enable input (active high) |
| 14 | CLOCK | Clock input (positive edge triggered) |
| 15 | RESET | Reset input (active low, resets count to 0 when low) |
| 16 | VDD | Positive supply (3V to 15V) |
The 10 decoded outputs Q0-Q9 are normally LOW. On the rising edge of the clock signal, the next output goes HIGH while the previous output goes LOW again. Only one decoded output is HIGH at a time.
The ENABLE input must be HIGH for the counter to increment on clock pulses. When ENABLE is LOW, the count is paused.
Applying a LOW signal to the active-low RESET input will reset the count to 0 (Q0 HIGH, Q1-Q9 LOW) irrespective of the clock signal.
The CARRY OUT pin goes HIGH when the counter rolls over from 9 to 0 (Q9 to Q0). This can be used to clock additional 4017 stages to make counters/dividers with a modulo higher than 10.
4017 Typical Operating Configurations
By connecting the CLOCK, ENABLE, and RESET inputs appropriately, the 4017 can be used in different operating modes:
Asynchronous Reset Mode
To reset the counter asynchronously (independent of the clock), the RESET pin is connected to an active-low reset signal. Whenever this reset signal goes LOW, the counter will reset to 0 immediately.
The ENABLE input must be tied HIGH for the counter to operate. The counter will advance on each rising edge of the clock signal applied to the CLOCK pin.
Gated Clock Mode
In this mode, the ENABLE pin is used to gate the clock signal. The counter advances on the positive clock edges only when ENABLE is HIGH.
With ENABLE LOW, the clock is inhibited and the counter holds its current state. The RESET pin is tied HIGH if not used.
Divide-by-N Mode
The 4017 can be configured as a divide-by-N counter by connecting the RESET pin to the appropriate decoded output QN-1.
For example, to divide by 6, RESET is connected to output Q5. The counter will count from 0 to 5 and then reset to 0 on the next clock pulse, since Q5 going HIGH will pull RESET LOW.
The ENABLE input must be HIGH. The divided down frequency is available at the selected output QN-1.
Some common divide ratios possible with a single 4017 and their RESET pin connections are:
| Division Ratio | RESET Connect To |
|---|---|
| ÷2 | Q1 |
| ÷3 | Q2 |
| ÷4 | Q3 |
| ÷5 | Q4 |
| ÷6 | Q5 |
| ÷7 | Q6 |
| ÷8 | Q7 |
| ÷9 | Q8 |
| ÷10 | Q9 |
Cascading Multiple 4017s
To achieve higher division ratios or more than 10 decoded outputs, multiple 4017s can be cascaded by connecting the CARRY output of one stage to the CLOCK input of the next.
For example, two 4017s can be cascaded to make a divide-by-100 counter or a 1-of-100 decoder with active HIGH outputs.
The first 4017’s CLOCK is driven by the input signal, and its CARRY output clocks the second 4017. Both counters are reset together by tying their RESET pins to the same signal (usually decoded output Q99). The ENABLE pins are tied HIGH.
The 100 decoded outputs are available on Q0-Q9 of the first 4017 for the first digit (1s place) and Q0-Q9 of the second 4017 for the second digit (10s place). Only one of these 100 outputs will be HIGH at a time. The final CARRY output (from second 4017) will go HIGH once per 100 input clocks.
In a similar manner, counters with an arbitrary count length can be made. For a modulo-N counter, N 4017s are cascaded, and the reset line is connected to QN-1 of the last stage. The CARRY output of this last stage provides a 1/N duty cycle output for the divided down frequency.
4017 Electrical Characteristics
The 4017 is a CMOS IC and has the typical characteristics of unbuffered CMOS logic:
- Wide supply voltage range: 3V to 15V
- Low power consumption: <1mW at 5V
- High input impedance: >1TΩ
- Relatively low output current: <1mA
- Transition times depend on load capacitance
- Maximum clock frequency depends on supply voltage (higher frequency at higher VDD)
- Inputs have fixed low and high threshold voltages (30% and 70% of VDD)
- Unused inputs should be tied to VDD or GND
- Outputs go to within a few millivolts of VDD and GND
Some key ratings and characteristics are:
| Parameter | Value |
|---|---|
| Supply voltage (VDD) | 3V to 15V |
| Input voltage | 0V to VDD |
| Storage temperature | -65°C to +150°C |
| Operating temperature | -40°C to +85°C |
| Output current (per pin) | 10mA |
| Power dissipation (package) | 500mW |
| Propagation delay (CLK to Q) | 60ns @ 5V |
| Maximum clock frequency (VDD=5V) | 5.5 MHz |
| Minimum clock pulse width (high or low) | 80ns @ 5V |
| Input low threshold | 30% of VDD |
| Input high threshold | 70% of VDD |
FAQ about the 4017
Q1: What happens if the ENABLE input is left floating?
A1: If the ENABLE input is left floating, it may cause erratic operation of the counter. Being a CMOS input, a floating input will cause the input to randomly drift between low and high states due to stray pickup. The counter may sporadically start and stop. Always tie the ENABLE input HIGH or LOW through a resistor.
Q2: What is the function of the CARRY OUT signal?
A2: The CARRY OUT signal goes HIGH when the counter rolls over from a count of 9 (Q9 HIGH) to 0 (Q0 HIGH) and remains high for 1 full clock cycle (until the end of Q0 being high). This signal is used to clock or cascade additional 4017 stages to build counters with a modulo higher than 10 (e.g. divide by 100 with two 4017s).
Q3: How can I make a 4017 based 1Hz oscillator for a clock?
A3: To make a 1Hz oscillator, a 4.194304MHz quartz crystal and a couple of 4017s can be used:
- Use the crystal with 2 inverters to make a 4.194304 MHz oscillator.
- Divide this frequency by 16 using a 4024 binary counter to get 262.144 kHz. This serves as the clock to the 4017 stages.
- Cascade two 4017 decade counters to divide by 100. Use the Q9 output of the second 4017 to get a 2621.44 Hz signal.
- Feed this 2621.44 Hz signal to the clock of a third 4017 configured to divide by 6 (reset it with Q5 output).
- The Q5 output of this last 4017 will be a 1.0168 Hz signal, which is accurate enough for most clock applications.
Q4: Can the 4017 work with a 555 oscillator?
A4: Yes, a 555 oscillator can definitely be used to clock the 4017 as long as the oscillator frequency is within the specifications of the 4017 (less than 5.5MHz at 5V VDD). The 555 can be configured as an astable multivibrator generating a precise 50% duty cycle clock signal. The frequency of this clock can be set using appropriate resistor and capacitor values.
Q5: How do I select the right output to connect the RESET pin for a divide-by-N configuration?
A5: For any desired division ratio N, the RESET pin should be connected to the QN-1 output (the output that is HIGH just before the desired rollover point).
For example:
– To divide by 2, connect RESET to Q1
– To divide by 5, connect RESET to Q4
– To divide by 7, connect RESET to Q6
– To divide by 10, connect RESET to Q9
This way, when the QN-1 output goes HIGH, it will immediately reset the counter to 0, effectively dividing the input frequency by N. Remember to keep ENABLE HIGH.
The 4017 decade counter/divider is a versatile chip for many digital logic circuits needing sequencing or frequency division. By understanding its features and configurations, it can be effectively used in a wide range of projects and applications.
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